This invention relates generally to communications technology, and more particularly, the invention relates to the interfacing of a broad band network to a lower bandwidth network fabric. In an illustrative application, a synchronous optical network (SONET) is interfaced with an asynchronous transfer mode (ATM) network fabric.
The communications industry is rapidly expanding in network technologies for the broad band transmission of voice, video and data. Two such technologies are SONET, which is a high speed synchronous carrier system based on the use of optical fiber technology, and ATM which is a high speed low delay multiplexing and switching network. SONET is high speed, high capacity and suitable for large public networks, whereas ATM is applicable to a broad band integrated services digital network (BISDN) for providing convergence, multiplexing, and switching operations.
Disclosed in FIG. 1A and in copending patent application 939A-358, supra, is a switch architecture including line interface units (LIMs) 2, a switch fabric 4, and a controller 6. The data path for cells traveling through an ATM network is to enter the line interface, pass through the fabric, and then exit through another line interface.
For signaling and management functions, cells are removed from the outgoing stream and sent to the controller. The controller can also transmit cells through the network by passing the cells to a LIM. The cells are then transmitted through the fabric and finally transmitted out an exit line interface. Passing control through the fabric before going to the controller or leaving the switch allows multiple controllers to each monitor a small number of line interfaces with call control and network management message passed to a centralized processor when the architecture is expanded to a larger number of ports.
FIG. 1B is a functional block diagram of a line interface which supports all by-line and by-connection functions including physical layer link termination, translation of ATM header information into routing tags for use by the fabric, policing of traffic, and cell rate decoupling (insertion and deletion of unassigned cells). The interface also measures cell loss, cells tagged, cells passed and the number of cells dropped for each connection. The controller configures and monitors the line interface and the fabric components, and also provides all call access control functions including call set-up, maintenance, and tear-down. It processes the information measured by the line interface to maintain connection and link statistics for network management.
FIG. 2 illustrates connection information in the ATM header and the switch cell header used internally within the switch itself. An ATM header contains a virtual path identifier (VPI) and a virtual circuit identifier (VCI) which together uniquely denote a single connection between two communicating entities. Other information, including a payload type and header error control fields, is included for use by the network in transporting the cells.
The switch header contains a connection identifier to denote the connection. A portion of the connection identifier may be replaced by a sequence number as described later in this document. Additionally, the switch header contains routing information so that the cell can be routed through the switch fabric 4 of FIG. 1A.
The ATM address translation and rate policing/shaping block (see FIG. 1B) converts cells between the two formats by mapping each bit pattern formed by a combination of VPI and VCI fields in the ATM header to a specific connection identifier in the internal switch header.
Therefore, cells that enter the switch have the ATM header removed and replaced with a switch header determined by the combination of the VPI and VCI fields in the ATM header. After those cells have been routed through the switch fabric, the switch header is replaced by an ATM header with the VPI and VCI fields set according to the value of the connection identifier.
FIG. 3 illustrates the switch fabric which routes cells to the proper outputs and maintains queue-level statistics on congestion, the number of cell periods during which backpressure is applied, and cell loss. The fabric is a 16 port buffered Benes interconnection network with 4.times.4 switch routing elements. In cell routing, as each cell passes through each individual switch routing element (SRE) from input to output, the SRE routes it to the proper output(s), depending on settings of bits within the routing tag. The fabric control port, which is directly connected to the control bus, allows the controller to program the SREs, and read their status. The fabric base clock (FBCLK) sets the rate at which data are acted on by the SREs, and transferred from one SRE to the next. This determines the internal link rate of the fabric.
As illustrated in FIG. 4, the switch routing element (SRE) is a 4.times.4 fully non-blocking routing element. Cells are clocked into each sync buffer at the rate they are transmitted by the sender. The data from the four sync buffers is multiplexed through the switch bus. The output selection blocks read the routing tag for each cell, and route the tag towards the respective output ports if the pattern matches the bit pattern for that port. Two levels of priority are supported by the output selection block. If its buffer fills beyond a programmable threshold, the output selection block may be programmed to SEND an overflow signal to the backpressure control block. Cells are simply dumped if the output selection block buffer overfills. Upon receiving a backpressure signal from outside the SRE, the output selection block may be programmed to ignore the signal, or slow the rate of data transfer through that port. Upon receiving a backpressure indication, the backpressure control block routes the signals to one or more sync buffers which synchronize the signal with the incoming data block.
Each SRE is individually addressed and maintains statistics on the number of cells dropped per output buffer, the number of cells tagged with FCI per output buffer, and the current state of each output buffer. Each output buffer can be programmed as to which type of routing field (selection or multitask) it uses and to where the routing field used for cell routing is located within the routing tag. This field can be read by the control processor. The SRE as a whole can be programmed to select a backpressure mode and this field can be read by the control processor.
The present invention is directed to a multiplexer/inverse multiplexer for use in a switch architecture as described above wherein the information to and from a high speed broad bandwidth network is transferred through a lower speed switch fabric. More particularly, the inverse multiplexing allows the use of switches that can be optimized for most common traffic rates.
In U.S. Pat. No. 5,065,396, a high rate data stream is split into multiple output connections into which timing signals are periodically inserted. At the destination, the timing signals are checked and used to multiplex the received signals into a single data stream. This approach works only on continuous data streams, like those found in T1 lines or SONET links. Furthermore, the approach requires that the transit delays of subpaths remain constant. The proposed approach allows both the rate of the inverse multiplex data stream to vary as well as the delays of the subpath.
In U.S. Pat. No. 5,317,561, the incoming data is split over multiple fabrics, with the individual cells marked with sequence numbers. At the output of the fabrics, the multiple streams are re-sequenced to produce the output. A primary disadvantage of this scheme is that multiple fabrics are required to carry a single port, rather than allowing multiple ports on the same fabric to be used for a higher rate connection. Another disadvantage is that only a single high rate data stream is split over the multiple ports.